Insulated gate planar integrated power device with co-integrated schottky diode and process

ABSTRACT

A process for integrating a Schottky contact inside the apertures of the elementary cells that constitute the integrated structure of the insulated gate power device in a totally self-alignment manner does not requires a dedicated masking step. This overcomes the limits to the possibility of increasing the packing density of the cellular structure of the integrated power device, while permitting improved performances of the co-integrated Schottky diode under inverse polarization of the device and producing other advantages. A planar integrated insulated gate power device with high packing density of the elementary cells that compose it, having a Schottky diode electrically in parallel to the co-integrated device, is also disclosed.

PRIORITY CLAIM

[0001] This application claims priority from European Patent ApplicationNo. 02425695.0, filed on Nov. 14, 2002, which is incorporated herein byreference.

TECHNICAL FIELD

[0002] The invention relates generally to insulated gate planarintegrated power devices and in particular to devices to which areassociated a power diode integrated on the same chip.

BACKGROUND

[0003] Insulated gate devices, such as MOSFETs in particular, are usedin many applications as synchronous rectifiers. In this case, theinsulated gate device operates as a diode: it is turned on when theequivalent diode must be in conduction and is turned off when the diodemust stop conducting.

[0004] This happens for example in output bridge stages in DC-DCconverter applications.

[0005] In these applications, the intrinsic bipolar diode (body-drainjunction) is switched, but such an intrinsic diode is inefficientbecause:

[0006] it switches slowly;

[0007] it has a high conduction voltage;

[0008] it may generate EMI in the board

[0009] and this limits the efficiency of the whole system.

[0010] In order to reduce the switching time or more precisely thereverse recovery time of the diode (trr), techniques for controlling thelife time of minority carriers are generally used. The introduction inthe semiconductor substrate of the device of Au, Pt, or other elementsby ion implantation, or irradiation with electrons, produces a markeddecrease of the life time (from tens of microseconds to tens ofnanoseconds) with consequent reduction of the trr of the intrinsic orinternal diode. In any case, the reduction of the trr is accompanied byan increase of the conduction voltage (Vf) and of the output resistance(Ron) of the insulated gate device that limits the usefulness of suchtechniques.

[0011] Moreover, these techniques amplify or do not reduce the problemsdue to a too fast recovery of the diode and thus to the emissions ofelectromagnetic interferences (EMI) on the board. In order to improvesoftness, more complex alternative techniques are needed.

[0012] A known approach is that of using a Schottky diode of the samevoltage and of appropriate area, in parallel to the internal PN junctiondiode of the integrated structure of the insulated gate device (forexample a power MOS transistor or briefly PMOS).

[0013] Because of the absence of minority carriers, the Schottky diodeis characterized by a fast recovery and, because of the differentbarrier heights, it has lower conduction voltages. In fact, for voltageslower than 0.9V the Schottky diode conducts a larger current than a PNjunction diode; for higher voltages, the characteristics become similarand the PN diode finally conducts a larger current, because of themodulation of its conductivity.

[0014] Therefore, the parallel of a junction diode and a Schottky diodeproduces an equivalent device with the following characteristics:

[0015] reduced Vf at relatively low current levels (<0.8V);

[0016] less stored charge and thus reduction of the switching time.

[0017]FIG. 1 illustrates the advantage of a combined diode MPS (MergedPN Schottky) in respect to a normal junction diode.

[0018] The experimental trade-off curve between Vf and the inversecurrent peak during the switching of a MPS diode upon varying the areaof the Schottky diode and when the control of the life time in a PNdiode has been obtained by irradiating the junction with high energyelectrons (3 MeV) at doses comprised between 0 and 32 MRad.

[0019] Nowadays, various Schottky diode configurations, in parallel withthe intrinsic diode of the PMOS structure are implemented in planardevices to be used in the low voltage range (320-150 V): that is fromthe simplest architecture that uses a single package but separatedevices (discrete solution) depicted in FIG. 2, to more complexarchitectures that integrate the Schottky diode in the PMOS structureitself.

[0020] Among known “integrated” solutions, there is the one shown inFIG. 3, according to which a separated area (on the same chip) isdedicated for the Schottky diode. However, this solution has limitationsand drawbacks, as will be explained later.

[0021] A more efficient solution, depicted in FIG. 4, consists in“distributing” the Schottky diode uniformly over the whole active areaof the PMOS by integrating it in the elementary cells of the MOS. It hasbeen demonstrated that by using a uniform distribution of Schottkydiodes, it is possible to improve the dynamic performances (trr andsoftness) while using a reduced total area dedicated to the diode.

[0022] A solution of this kind, for low voltages devices, is disclosedin the U.S. Pat. No. 5,886,383.

[0023] According to the technique described in the patent, a Schottkydiode is realized in the elementary cell of the MOSFET by a dedicatedstep of photolithography for realizing a Schottky diode through acertain aperture produced through a first deposited polysilicon layer,that is in the area destined to the realization of the integratedstructure of an elementary cell of the insulated gate power device andon which the relative source contact will be established.

[0024] Commonly, Schottky diodes are realized by contacting with a metallayer the monocrystalline semiconducting substrate, the doping level ofwhich determines the voltage class. In order to improve electriccharacteristics (leakage and breakdown voltage) when not conducting, itis well known the technique of forming, around the Schottky contactregion in the semiconductor, a more or less dense array of juxtaposeddiffuse regions (tubs) of opposite type of conductivity to that of thesubstrate (Lateral Merged PiN Schottky). The distance of separationamong adjacent tubs is chosen so that under conditions of inversepolarization, the electric field is partially shielded by the depletedzones that form around the tubs.

[0025] Summarizing, in order to co-integrate Schottky diodes within thecellular structure of a power MOS there are two different approaches:

[0026] 1) Schottky diode formed in dedicated areas inside the power MOS.In this case, areas more or less distributed are defined within theactive area of the MOS structure, on which a Schottky contact isrealized through the process steps that are done for realizing theintegrated MOS structure. As explained before, in order to limit leakagecurrent, the Schottky diode contact is surrounded by diffusions ofopposite type of conductivity to that of the semiconductor crystal forshielding the electric field that is created under inverse polarization.The shielding diffusions may be realized by the same body implant of theMOS or by a dedicated implant step.

[0027] 2) Schottky diode integrated in the single elementary cells thatconstitute the power MOS. Even if more efficient, this approach islittle used because it imposes layout restraints severely limiting thepossibility of increasing the packing density. The known techniques,such as the technique described in the above mentioned U.S. Pat. No.5,886,383, require the realization of an island (51 of FIG. 4) of oxideor photoresist within an aperture produced through the polysilicon layer(poly). This limits the possibility of reducing the width of theaperture and represents an obstacle to increase the packing density ofthe elementary cells of the integrated structure of the power device.The shielding diffusions of the Schottky diode must necessarily berealized with the same implant step of the body of the MOS.

SUMMARY

[0028] There exists the need of integrating a Schottky diode in anelementary cell of an integrated structure of an insulated gate powerdevice without limiting the possibility of reducing the dimensions(scaling down) of the elementary cell apart from the resolution of thephoto-exposition equipment and the precision of localization of thedopants implanted in the semiconducting substrate crystal of theavailable fabrication technology.

[0029] A further aspect of the present invention is that of limiting thenumber of photolithographic steps in the sequence of process steps of aninsulated gate integrated power device with co-integrated Schottky diodein parallel thereto.

[0030] The above mentioned aspects and other important advantages areobtained with the fabrication process and the integrated structureaccording to the disclosed embodiments of the present invention.

[0031] According to an embodiment of the present invention, thephotolithographic step for defining the Schottky contact area inside theaperture of a discrete or of an elementary cell of an integratedstructure of the insulated gate power device, is eliminated by carryingout:

[0032] 1) an ion implantation of dopants for realizing a diffused bodyregion with appropriate tilt and twist angles through the cell apertureformed in the layer of polysilicon deposited beforehand;

[0033] 2) an ion implantation of dopants for realizing a sourcediffusion on the whole area of the aperture through the polysilicon; and

[0034] 3) formation of a spacer along the lateral walls of the cellaperture through the polysilicon to define the anisotropic etching areaof the semiconductor crystal.

[0035] In practice, an embodiment of the invention provides a method forintegrating a Schottky contact inside the apertures of the elementarycells that constitute the integrated structure of the insulated gatepower device in a totally self-alignment manner without requiring adedicated masking step. This overcomes the above indicated limits to thepossibility of increasing the packing density of the cellular structureof the integrated power device, while permitting improved performancesof the co-integrated Schottky diode under inverse polarization of thedevice and producing other advantages that will be mentioned in theensuing description.

[0036] A planar integrated insulated gate power device with high packingdensity of the elementary cells that compose it, having a Schottky diodeelectrically in parallel to the co-integrated device in each cell areadefined by an aperture produced through a gate polysilicon layerdeposited beforehand and that is insulated from the underlyingsemiconductor crystal by a dielectric gate layer, and through which theintegrated structure and the respective source contact of an elementarycell is constituted, has an elementary cell structure that comprises, onthe surface of the semiconducting substrate single crystal, an implantedand diffused body region and an invertible channel region under theinsulated gate electrode constituted by the polysilicon layer, forestablishing inversion conditions in said channel region. An implantedand diffused source region is formed in the cell area within the bodyregion. A drain region of the semiconductor substrate is coupled to theinvertible channel region and the current is eventually collectedthrough a drain contact.

[0037] According to an embodiment of this invention, a trench is formed,in self-alignment to spacers formed on definition edge surfaces of theaperture, in the semiconductor crystal in a portion of the area of theaperture that includes a central “window” that is defined in a shadepattern by purposely implanting with different tilt and twist angles thebody dopants, for a depth extending from the crystal surface through thesource region and the body region that surrounds the central zone ofsaid window not implanted with the body dopants, reaching down into thedrain semiconductor under the source diffusion in correspondence of saidwindow. A deposited metal layer contacts on at least a portion of theside walls of the trench, the source, and the body region, constitutinga source contact, and, on the bottom of the trench, the drainsemiconductor substrate thus establishing a Schottky contact with thedrain region, electrically in parallel to the insulated gate device.

[0038] In other words, said trench is formed in a central zone of thearea of the cell aperture and of the diffused body region, for a depthsufficient to reach into the semiconductor beyond the bottom profile ofthe source diffusion, that is in a region electrically coinciding withthe drain region and surrounded by the diffused body region. The sourcecontact metallization fills the trench establishing an electric contactwith the source region and with the body region on at least a portion ofthe surface of the side walls of the trench and a Schottky contact on atleast a portion of the bottom surface of the trench.

[0039] According to an alternative embodiment of this invention, thestructure further comprises a diffused deep body region, more heavilydoped than the first diffused body region that is contained therein.This second or deep body region besides containing the first bodyregion, extends for a greater depth than the first body region surrounda deeper zone under the Schottky contact established on the bottom ofthe trench.

[0040] According to yet another alternative embodiment of thisinvention, the structure further comprises a buried region having thesame type of conductivity of the first body region, geometricallylocated in the semiconductor crystal at a certain depth under theSchottky contact established on the bottom of the trench and surroundedby a deep body region and/or by the body region.

[0041] The invention and the various embodiments thereof are moreprecisely defined in the annexed claims and the detailed description,respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The different aspects and advantages of this invention willappear even more evident through the following description of severalalternative embodiments and referring to the attached drawings wherein:

[0043]FIG. 1 shows the experimental trade-off curve between the voltageVf and the inverse current peak of a switching MPS diode, with anirradiated PN junction diode in function of the area reserved to theSchottky diode;

[0044]FIG. 2 depicts a solution with discrete elements combined in asingle package;

[0045]FIG. 3 depicts a monolithic solution with distinct areas for thePMOS and the Schottky diode;

[0046]FIG. 4 depicts an integrated solution of a Schottky diode in eachelementary cell of the PMOS, according to the prior art;

[0047] FIGS. from 5 to 14 illustrate the relevant steps of a process offabrication of an insulated gate power device and characteristics of thestructure that is realized, according to a first embodiment of thisinvention;

[0048] FIGS. from 15 to 21 illustrate the relevant steps of a process offabrication and characteristics of the structure that is realized,according to an alternative embodiment of this invention;

[0049]FIG. 22 shows leakage characteristics under inverse polarizationin function of the area of the Schottky contact in the embodiments ofFIGS. 5-14 and 15-21;

[0050] FIGS. from 23 to 29 illustrate the relevant steps of a process offabrication and characteristics of the structure that is realized,according to a third alternative embodiment of this invention;

[0051]FIG. 30 shows the inverse leakage and the direct voltage dropperformances in function of the characteristics of a shielding buriedregion of the Schottky contact in the embodiment of FIGS. 23-29.

DETAILED DESCRIPTION

[0052] The following discussion is presented to enable a person skilledin the art to make and use the invention. Various modifications to theembodiments will be readily apparent to those skilled in the art, andthe generic principles herein may be applied to other embodiments andapplications without departing from the spirit and scope of the presentinvention. Thus, the present invention is not intended to be limited tothe embodiments shown, but is to be accorded the widest scope consistentwith the principles and features disclosed herein.

[0053] Making reference to the FIGS., the integrated structure of thisinvention and the way in which it may be realized according toembodiments of this invention will be described herein below.

[0054] Basically, the process of this invention differs from the knownprocesses for the realization of a structure of an insulated gate devicewith Schottky diode integrated in the elementary cells that compose thedevice, because of the way in which the elementary cell structure isrealized such to include a Schottky contact between the source metallayer and a region of semiconductor crystal of substrate electricallycoinciding with the drain of the integrated power device.

[0055] The process steps that characterize embodiments of the inventionmay be introduced in any process flow for the fabrication of anintegrated floating gate power device, such as a power MOS or brieflyPMOS. For this reason, specific dimensional details of structuralfeatures and relative doses and implantation energies of the dopants arenot indicated, given that these may vary from one process to anotherdepending on fabrication technology, particular needs and/or preferencesof the manufacturer.

[0056] Moreover, only for illustrating purposes, the realization of anN-channel PMOS is shown, though it is intended that the structure ofthis invention may also be that of a P-channel floating gate device, bysimply inverting, in a dual mode, the type of conductivity of thesemiconducting crystal substrate and of the dopants used for realizingthe various diffused regions.

[0057] Basic process sequence (FIGS. 5 to 14)

[0058] 1. realization of the drain semiconducting substrate and of theedge structure of the integrated insulated gate power device accordingto any known process;

[0059] 2. realization of the insulated gate according to any knownprocess (growth or deposition of a dielectric gate oxide film anddeposition thereon of a conducting layer of polycrystalline silicon(polysilicon));

[0060] 3. covering of the conducting gate electrode layer of polysiliconwith an insulating layer of a dielectric material (for example a layerof 0.5 μm of LTO);

[0061] 4. covering with photosensitive material of appropriate thickness(for example a layer of 1.5 μm of a photoresist);

[0062] 5. definition of the gate electrode of polysilicon byphotolithography of the layer photoresist followed by selectiveanisotropic etching first of the insulating layer and then of thepolysilicon (on grounds of expediency a stripe cellular layout may bepreferable (that is each cell is defined in the form of a short segmentof a definition line, but of course this embodiment of the invention maybe practiced with any other type of cellular layout);

[0063] 6. ion implantation (first body implant) with appropriate tiltand twist angles of a P type dopant (for example boron or indium with30° tilt and 90° twist). The tilt angle must be chosen such to create ashade zone by the windows opened by the anisotropic (vertical) etchingin the stack composed of the polysilicon layer and the insulating layer.The tilt angle to be used will depend from the total height of theetched edge of the hard mask formed by the polysilicon the insulatinglayer and eventually also of the residual thickness of the photo resistmask, and from the width of the stripes or definition lines. The twistangle must be such to make the impinging ion beam orthogonal to the longside of the stripe segments. The implant dose and energy will be chosensuch to obtain the desired concentration and channel length;

[0064] 7. ion implantation (second body implantation) of the same P typedopant but with tilt and twist angles opposite to the ones of thepreceding implantation step (for example boron or indium with −30° tiltand 90° twist or 30° tilt and −90° twist);

[0065] 8. removing of the mask of photoresist;

[0066] 9. activation of the body dopants (for example, 30 seconds inoven at 1100° C.);

[0067] 10. ion implantation (source implant) of a N type dopant (forexample 1015 ions/cm2 of arsenic with an implant energy of about 80keV);

[0068] 11. activation of the source dopant (for example, 30 seconds inoven at 1100° C.);

[0069] 12. covering with one or more layers of a dielectric insulatingmaterial deposited in a sufficient conformal mode on the cell areadefinition steps;

[0070] 13. anisotropic (vertical) etching of the layer of insulatingmaterial deposited for forming a spacer over the definition edges of thecell area stripes;

[0071] 14. anisotropic (vertical) etching of the silicon for a depthdeeper than the depth of the doped source region but shallower than thedepth of the doped body regions. The so realized microtrench exposeswithin the area of each cell of the integrated structure of the PMOS,silicon surfaces of the doped source regions, the doped body regions andat the bottom of the trench also the surface of the silicon of substratebetween the body diffusions, that coincides electrically with the drainof the PMOS;

[0072] 15. opening by means of a dedicated photolithography of the gatecontacts;

[0073] 16. metallization of the front side of the wafer with a materialcapable of establishing a good electrical contact with said exposedsurfaces of the body and source diffusions and a good barrier height ofthe Schottky contact that is established at the bottom of the trenchwith the silicon of substrate, that is with the drain of the integratedstructure of the insulated gate power device (suitable materials may befor example titanium or a silicide thereof);

[0074] 17. finishing of the front side and of the rear side according tothe common fabrication process.

[0075] Even if it is possible to realize the body regions with only twotilted implantations, it may happen that the charge under the source beinsufficient in certain particular applications to prevent the turningon of the parasitic transistor that is created by the source/body/drainjunctions.

[0076] In order to increase robustness, it is advisable for certainapplications to perform a second pair of tilted implantations forenriching the body zones under the source, in practice realizing asecond or deep body diffused region.

[0077] Process sequence with formation of an additional deep body region(FIGS. 15 to 21)

[0078] 1. realization of the drain semi conducting substrate and of theedge structure of the integrated insulated gate power device accordingto any known process;

[0079] 2. realization of the insulated gate according to any knownprocess (growth or deposition of a dielectric gate oxide film anddeposition thereon of a conducting layer of polycrystalline silicon(polysilicon));

[0080] 3. covering of the conducting gate electrode layer of polysiliconwith an insulating layer of a dielectric material (for example a layerof 0.5 μm of LTO);

[0081] 4. covering with photosensitive material of appropriate thickness(for example a layer of 1.5 μm of a photo resist);

[0082] 5. definition of the gate electrode of polysilicon byphotolithography of the layer photo resist followed by selectiveanisotropic etching first of the insulating layer and then of thepolysilicon (on grounds of expediency a stripe cellular layout may bepreferable (that is each cell is defined in the form of a short segmentof a definition line, but of course the invention may be practiced withany other type of cellular layout);

[0083] 6. ion implantation (first deep body implantation) withappropriate tilt and twist angles of a P type dopant (for example boronor indium with 20° tilt and 90° twist). The tilt angle must be chosensuch to create a shade zone in the windows opened by the anisotropic(vertical) etching through the stack composed of the polysilicon layerand the insulating layer. The tilt angle to be used will depend from thetotal height of the etched edge of the mask formed by the polysiliconlayer, the insulating layer and the residual thickness of the photoresist mask, and from the width of the stripes or definition lines. Thetwist angle must be such that the ionic stream be orthogonal to the longside of the stripes. The dose and the implant energy must be chosen suchto obtain the desired concentration;

[0084] 7. ion implantation (second deep body implant) of the same P typedopant but with tilt and twist angles opposite to those of the precedingimplantation step (for example boron or indium with −20° tilt and 90°twist or 20° tilt and −90° twist);

[0085] 8. removing of the mask of photo resist;

[0086] 9. ion implantation (first body implant) with appropriate tiltand twist angles of a P type dopant (for example boron or indium with40° tilt and 90° twist). The tilt angle must be chosen such to create ashade zone by the windows opened by the anisotropic (vertical) etchingin the stack composed of the polysilicon layer and the insulating layer.The tilt angle to be used will depend from the total height of theetched edge of the hard mask formed by the polysilicon the insulatinglayer and from the width of the stripes or definition lines. The twistangle must be such to make the impinging ion beam orthogonal to the longside of the stripe segments. The implant dose and energy will be chosensuch to obtain the desired concentration and channel length;

[0087] 10. ion implantation (second body implantation) of the same Ptype dopant but with tilt and twist angles opposite to those of thepreceding implantation step (for example boron or indium with −40° tiltand 90° twist or 40° tilt and −90° twist);

[0088] 11. activation of the dopants (for example, 30 seconds in an ovenat 1100° C.);

[0089] 12. ion implantation (source implant) of a N type dopant (forexample 1015 ions/cm2 of arsenic with an implant energy of 80 keV);

[0090] 13. activation of the source dopant (for example, 30 seconds inoven at 1100° C.);

[0091] 14. covering with one or more layers of a dielectric insulatingmaterial deposited in a sufficient conformal mode on the cell areadefinition steps;

[0092] 15. anisotropic (vertical) etching of the layer of insulatingmaterial deposited for forming a spacer over the definition edges of thecell area stripes;

[0093] 16. anisotropic (vertical) etching of the silicon for a depthdeeper than the depth of the doped source region but shallower than thedepth of the doped body regions. The so realized micro trench exposeswithin the area of each cell of the integrated structure of the PMOS,silicon surfaces of the doped source regions, the doped body regions andat the bottom of the trench also the surface of the silicon of substratebetween the body diffusions, that coincides electrically with the drainof the PMOS;

[0094] 17. opening by means of a dedicated photolithography of the gatecontacts;

[0095] 18. moralization of the front side of the wafer with a materialcapable of establishing a good electrical contact with said exposedsurfaces of the body and source diffusions and a good barrier height ofthe Schottky contact that is established at the bottom of the trenchwith the silicon of substrate, that is with the drain of the integratedstructure of the insulated gate power device (suitable materials may befor example titanium or a silicate thereof);

[0096] 19. finishing of the front side and of the rear side according tothe common fabrication process.

[0097] It has been noticed that the presence of a Schottky contactsensibly worsen the reverse bias electrical characteristics of theintegrated device. As may be observed from the characteristics of FIG.22, the leakage current varies by orders of magnitude in function of thepercentage of cell area that is dedicated to the Schottky contact.

[0098] In order to reduce the adverse effect on the leakage current ofthe presence of a co-integrated Schottky diode, according to an optionalembodiment of this invention, an implantation (which hereinafter will bereferred to as “drain engineering” or D.E.) is included in the processsequence for increasing the resistivity of the semiconductor ofsubstrate (drain) of the device under the Schottky contact region.

[0099] Of course, the semiconductor substrate or drain may be inpractice an expitaxial layer grown on a semiconductor crystal that mayhave electrical characteristics different from those of the epitaxiallayer grown thereon.

[0100] An implanted buried region of “drain engineering” will beelectrically tied to the body or, where they exists, to the deep bodydiffusions, such to effectively shield the Schottky contact also in avertical direction, with the result of decisively reducing the leakagecurrent.

[0101] According to this optional embodiment, the realized integratedstructure may be defined as “Lateral & Vertical Merged PiN Schottky(LVMPS)”.

[0102] Process sequence with buried region of “drain engineering” (FIGS.23 to 29)

[0103] 1. realization of the drain semiconducting substrate and of theedge structure of the integrated insulated gate power device accordingto any known process;

[0104] 2. realization of the insulated gate according to any knownprocess (growth or deposition of a dielectric gate oxide film anddeposition thereon of a conducting layer of polycrystalline silicon(polysilicon));

[0105] 3. covering of the conducting gate electrode layer of polysiliconwith an insulating layer of a dielectric material (for example a layerof 0.5 μm of LTO);

[0106] 4. covering with photosensitive material of appropriate thickness(for example a layer of 1.5 μm of a photo resist);

[0107] 5. definition of the gate electrode of polysilicon byphotolithography of the layer photo resist followed by selectiveanisotropic etching first of the insulating layer and then of thepolysilicon (on grounds of expediency a stripe cellular layout may bepreferable (that is each cell is defined in the form of a short segmentof a definition line, but of course the invention may be practiced withany other type of cellular layout);

[0108] 6. ion implantation (Drain Engineering implant) at high energy ofa P type dopant (for example boron at 200-400 keV). The dose to beimplanted must be such to compensate slightly the epitaxial layer and itis thus a function of the voltage class of the power device beingfabricated;

[0109] 7. ion implantation (first body implant) with appropriate tiltand twist angles of a P type dopant (for example boron or indium with30° tilt and 90° twist). The tilt angle must be chosen such to create ashade zone by the windows opened by the anisotropic (vertical) etchingin the stack composed of the polysilicon layer and the insulating layer.The tilt angle to be used will depend from the total height of theetched edge of the hard mask formed by the polysilicon the insulatinglayer and eventually also of the residual thickness of the photo resistmask, and from the width of the stripes or definition lines. The twistangle must be such to make the impinging ion beam orthogonal to the longside of the stripe segments. The implant dose and energy will be chosensuch to obtain the desired concentration and channel length;

[0110] 8. ion implantation (second body implant) of the same P typedopant but with tilt and twist angles opposite to those of the precedingimplantation (for example boron or indium with −30° tilt and 90° twistor 30° tilt and −90° twist);

[0111] 9. removing of the mask of photo resist;

[0112] 10. activation of the body dopants (for example, 30 seconds inoven at 1100° C.);

[0113] 11. ion implantation (source implant) of a N type dopant (forexample 1015 ions/cm2 of arsenic with an implant energy of about 80keV);

[0114] 12. activation of the source dopant (for example, 30 seconds inoven at 1100° C.);

[0115] 13. covering with one or more layers of a dielectric insulatingmaterial deposited in a sufficient conformal mode on the cell areadefinition steps;

[0116] 14. anisotropic (vertical) etching of the layer of insulatingmaterial deposited for forming a spacer over the definition edges of thecell area stripes;

[0117] 15. anisotropic (vertical) etching of the silicon for a depthdeeper than the depth of the doped source region but shallower than thedepth of the doped body regions. The so realized micro trench exposeswithin the area of each cell of the integrated structure of the PMOS,silicon surfaces of the doped source regions, the doped body regions andat the bottom of the trench also the surface of the silicon of substratebetween the body diffusions, that coincides electrically with the drainof the PMOS;

[0118] 16. opening by means of a dedicated photolithography of the gatecontacts;

[0119] 17. moralization of the front side of the wafer with a materialcapable of establishing a good electrical contact with said exposedsurfaces of the body and source diffusions and a good barrier height ofthe Schottky contact that is established at the bottom of the trenchwith the silicon of substrate, that is with the drain of the integratedstructure of the insulated gate power device (suitable materials may befor example titanium or a silicate thereof);

[0120] 18. finishing of the front side and of the rear side according tothe common fabrication process.

[0121] Advantages:

[0122] a) the composite basic cell structure MOS+Schottky of thisinvention is realized without any additional dedicated masking step. Thewidth of the stripes is thus limited only by the resolution of thephotoexposition equipment and by the ability to precisely implant thedopants (to this end it is convenient to use dopants with lowdiffusivity such as indium and arsenic);

[0123] b) by carrying out a process flow that contemplates the formationof an additional buried drain engineering region, a reduction of theleakage current of even an order of magnitude may be achieved whileretaining all advantages under direct bias (FIG. 30).

[0124] Though embodiments of the invention have been illustrated for thecase of fabrication of a N channel PMOS, the invention can be practicedalso for fabricating a P channel PMOS, by inverting the types ofdopants.

[0125] Of course, the use of a stripe layout is not mandatory, othercellular layouts may be used, eventually performing several pairs ofbody implantations each with appropriate tilts and twist angles in orderto realize the body diffusions in each channel zone while defining aShottky contact window there between.

[0126] The formation of a self-aligned Schottky contact in a “window”defined by the use of angled implantations in the middle of the cellarea, may be extended even to a structure with traditional contacts(that is defined and opened by photolithography). In this case theetching of silicon for forming the microtrench will not be self-alignedto the window opened by photolithography through the polysilicon, butself-aligned to the contact openings.

[0127] Even the concept of “Lateral & Vertical Merged PiN Schottky(LVMPS)”, that is the introduction of an implantation (buried region)under the lateral body diffusions and under the Schottky contact region,for modifying locally the doping profile of the drain, may be extendedalso to Schottky diodes that are not co-integrated in the elementarycells of the integrated power device, but realized in dedicated areas.

[0128] The graph of FIG. 30 shows the leakage current and the directvoltage drop obtained on test structures for different doses of drainengineering dopant. Near the dose of 2*1012 ions/cm2 there is enoughroom for reducing the leakage by an order of magnitude without burdeningexcessively the direct voltage drop. By doubling the dose, the drainengineering diffusion creates a junction that shields the Schottkycontact but reduces the direct characteristic to become practicallysimilar to that of a PN junction diode.

[0129] The insulated gate planar power devices avcording to the aboveembodiments may be used in a variety of different types of electronicsystems, such as a DC-DC converter and other types of rectifyingsystems.

[0130] Even though various embodiments and advantages of the resentinvention have been set forth in the foregoing description, the abovedisclosure is illustrative only, and changes may be made in detail andyet remain within the broad principals of the present invention.Therefore, the present invention is to be limited oly by the appendedclaims.

1. An insulated gate planar power device with high packing density ofthe elementary cells that compose it, having a co-integrated Schottkydiode electrically in parallel to the device formed in the area of eachcell defined by an aperture through a polysilicon gate electrode,insulated from the underlying semiconductor by a dielectric gate layer,and through which such a co-integrated cell structure is constituted,each elementary cell comprising a body region formed in thesemiconductor coupled to an invertible channel region under saidinsulated polysilicon gate electrode for establishing conditions ofinversion of said channel region, a source region formed in the area ofsaid cell aperture within said body region, a drain region in saidsemiconductor coupled to said invertible channel region, a trench formedin said semiconductor in a portion of the area of said cell aperturehaving a depth extending from the surface of the semiconductor throughsaid source region and said body region, a source metal layer contactingover the sides of said trench said source region and said body regionfor establishing a source contact and said drain region at the bottom ofsaid trench to establish a Schottky diode contact, electrically inparallel to the elementary cell of the integrated insulated gate device,characterized in that said trench is self aligned to dielectric spacersformed on the definition edges surfaces of said aperture in a portion ofthe area of the aperture that includes a central “window” defined in ashade pattern of slanted body dopants implant, for a greater depth thanthe bottom of said source region and sufficient to expose at the bottomof the trench said drain region in the semiconductor bordered by saidbody region at least along two opposite sides; said contact metal fillssaid central trench establishing an electric contact with said sourceregion and with said body region on at least a portion of the surface ofthe lateral sides of said trench and said Schottky contact on at least aportion of the bottom surface of said trench.
 2. The device of claim 1,characterized in that it further comprises a second deep body region,more heavily doped of said first body region, laterally contained insaid first body region, but extending in said semiconductor for agreater depth than said first region, for shielding deeper the drainzone under said Schottky contact at least along two opposite sides. 3.The device of claim 1, characterized in that it further comprises, insaid semiconductor, a buried region having the same type of conductivityof said first body region, formed under and at a depth from saidSchottky contact established at the bottom of said trench.
 4. The deviceof any of the claims from 1 to 3, characterized in that said drainregion in said semiconductor is an epitaxial layer grown on asemiconducting crystal with electrical characteristics different fromthat of said epitaxially grown layer.
 5. The device of any of the claimsfrom 1 to 4, characterized in that it is a N channel device.
 6. Aprocess for fabricating an insulated gate integrated power devicecomprising the steps of: a) constituting a drain semi conductingsubstrate doped with a dopant of a first type of conductivity andforming an edge structure of the insulated gate integrated power device,b) forming an insulated gate electrode by growing or depositing adielectric film of gate oxide on the surface of said drainsemiconducting substrate and depositing thereon a conductive layer ofpolysilicon, c) covering said conductive polysilicon layer with aninsulating layer or multilayer of dielectric material deposited thereon,d) depositing a layer of photo resist on said deposited insulatinglayer, e) defining said gate electrode by masking and anisotropicselective etching of said deposited insulating layer and of saidpolysilicon layer forming apertures through the area of which theintegrated structure and the relative source contact of each elementarycell constituting said power device will be formed, and characterized inthat the successive sequence comprises the steps of f) performing afirst ion implantation of a dopant appropriate to constitute a bodyregion of opposite type of conductivity of said drain semiconductingsubstrate with certain tilt and twist angles such to determine a shadezone inside said aperture in function of the total height of thedefinition edge of the stack composed of said polysilicon layer, saidinsulating layer and said layer of photo resist, and of the width of theaperture, with an implant dose and energy appropriate to obtain acertain concentration and channel length; g) performing at least asecond ion implantation at the same conditions of said firstimplantation but with different tilt and twist angles to define acentral window in the shade pattern on the implanted cell area; h)removing of said layer of photo resist; i) activating the implanteddopants by heat treatment; j) performing a source ion implantation onthe whole area of said aperture of a dopant of the same type ofconductivity of the drain substrate and opposite to that of the dopantof said body implantations with dose and energy of implant appropriateto constitute a source region surrounded by said body region; k)activating of the implanted source dopant by heat treatment; l)depositing a sacrificial layer of a dielectric material under conditionsof substantial uniformity of thickness of deposition over the steps ofthe definition borders of said apertures; m) anisotropic etching of thesacrificial layer for leaving a dielectric spacer on the definition edgesurfaces of said apertures; n) anisotropic etching of the semiconductorfor a depth deeper than the depth of said source region but shallowerthan the depth of said body region, exposing within the area of eachcell surfaces of said source region, of said body region and, at thebottom of the trench, a zone of said drain substrate surroundedlaterally by said body region; o) opening of contacts on said gateelectrode through a dedicated photo resist mask; p) removing the photoresist mask and depositing one or more conductive metal layers forestablishing inside said trench an electric contact with both the sourceregion and the body region and determining a good barrier height of theSchottky contact established with the drain substrate on at least aportion of the bottom surface of said trench.
 7. A process forfabricating an insulated gate integrated power device comprising thesteps of: a) constituting a drain semi conducting substrate doped with adopant of a first type of conductivity and forming an edge structure ofthe insulated gate integrated power device, b) forming an insulated gateelectrode by growing or depositing a dielectric film of gate oxide onthe surface of said drain semi conducting substrate and depositingthereon a conductive layer of polysilicon, c) covering said conductivepolysilicon layer with an insulating layer or multilayer of dielectricmaterial deposited thereon, d) depositing a layer of photo resist onsaid deposited insulating layer, e) defining said gate electrode bymasking and anisotropic selective etching of said deposited insulatinglayer and of said polysilicon layer forming apertures through the areaof which the integrated structure and the relative source contact ofeach elementary cell constituting said power device will be formed, andcharacterized in that the successive sequence comprises the steps of f)performing a first ion implantation of a dopant appropriate toconstitute a deep body region of opposite type of conductivity of saiddrain semi conducting substrate with certain tilt and twist angles suchto determine a shade zone inside said aperture in function of the totalheight of the definition edge of the stack composed of said polysiliconlayer, said insulating layer and said layer of photo resist, and of thewidth of the aperture, with an implant dose and energy appropriate toobtain a certain concentration and depth of implant; g) performing atleast a second ion implantation at the same conditions of said firstimplantation but with different tilt and twist angles to define acentral window in the shade pattern on the implanted cell area; h)removing said layer of photo resist; i) performing at least a third ionimplantation of a dopant appropriate to constitute a body region ofopposite type of conductivity of said drain semi conducting substratewith certain tilt and twist angles such to determine a shade zone insidesaid aperture in function of the total height of the definition edge ofthe stack composed of said polysilicon layer and said insulating layer,and of the width of the aperture, with an implant dose and energyappropriate to obtain a certain concentration and channel length; j)performing at least a fourth ion implantation at the same conditions ofsaid third implantation but with different tilt and twist angles todefine a central window in the shade pattern on the implanted cell areak) activating the implanted body and deep body dopants by heattreatment; l) performing a source ion implantation on the whole area ofsaid aperture of a dopant of the same type of conductivity of the drainsubstrate and opposite to that of the dopants of said body and deep bodyimplantations, with dose and energy of implant appropriate to constitutea source region surrounded by said body region; m) activating theimplanted source dopant by heat treatment; n) depositing a sacrificiallayer of a dielectric material under conditions of substantialuniformity of thickness of deposition over the steps of the definitionborders of said apertures; o) anisotropic etching of the sacrificiallayer for leaving a dielectric spacer on the definition edge surfaces ofsaid apertures; p) anisotropic etching of the semiconductor for a depthdeeper than the depth of said source region but shallower than the depthof said body region, exposing within the area of each cell surfaces ofsaid source region, of said body region, and, at the bottom of thetrench, said deep body region and a zone of said drain substratesurrounded laterally by said deep body region; q) opening of contacts onsaid gate electrode through a dedicated photo resist mask; r) removingthe photo resist mask and depositing one or more conductive metal layersfor establishing inside said trench an electric contact with both thesource region and the body region and determining a good barrier heightof the Schottky contact established with the drain substrate on at leasta portion of the bottom surface of said trench.
 8. A process offabrication of a device according to claim 6 or 7, characterized in thatit comprises the further step of carrying out, after having defined thegate electrode with the formation of said apertures, an ion implantationat sufficiently high energy for implanting a dopant of the same type ofconductivity of the dopant used for realizing said body region in aburied region at a depth deeper than the bottom of said body regions,with a dose insufficient to compensate completely the dopantconcentration of opposite type of conductivity of said drain substrateto create a shielding region under the Shottky contact.
 9. An insulatedgate planar power device with a Schottky diode in parallel thereto, saidShottky diode being realized by contacting with a metal layer asemiconductor substrate of a first type of conductivity and the contactzone being laterally surrounded by one or more diffused regions ofopposite type of conductivity formed in said substrate for shielding theelectric field under conditions of reverse bias of the diode,characterized in that it comprises, in said semiconducting substrate, aburied region doped with a dopant of opposite type of conductivity tothat of said semiconductor substrate, geometrically located under saidSchottky contact zone and at a greater depth than the depth of saiddiffused regions.
 10. The device of claim 9, wherein said buried regionhas the same type of conductivity of the semiconducting substrate buthas a reduced resultant doping level.
 11. A process of fabrication of aninsulated gate planar power device according to claim 9, comprising thesteps of: a) constituting a drain semi conducting substrate of a firsttype of conductivity, b) forming an insulated gate electrode by growingor depositing a dielectric film of gate oxide on the surface of saiddrain semiconducting substrate and depositing a conductive polysiliconlayer; c) covering said polysilicon layer with an insulating layer ofdielectric material deposited thereon, d) depositing a layer of photoresist on said insulating layer, e) defining said gate electrode bymasking and anisotropic selective etching of said deposited insulatinglayer and of said polysilicon layer forming apertures through the areaof which discrete structures or elementary cell of integrated structuressaid power device will be formed, and characterized in that thesuccessive sequence comprises the steps of f) performing a first ionimplantation of a dopant appropriate to constitute a body region ofopposite type of conductivity of said drain semi conducting substratewith certain tilt and twist angles such to determine a shade zone insidesaid aperture in function of the total height of the definition edge ofthe stack composed of said polysilicon layer, said insulating layer andsaid layer of photo resist, and of the width of the aperture, with animplant dose and energy appropriate to obtain a certain concentrationand channel length; g) performing at least a second ion implantation atthe same conditions of said first implantation but with different tiltand twist angles to define a central window in the shade pattern on theimplanted cell area; h) performing at least a third ion implantation atsufficiently high energy for implanting a dopant of the same type ofconductivity of the dopant used to realize said body regions in a buriedregion at a greater depth than that of the bottom of said body regions,of and in a dose insufficient to compensate completely the dopantconcentration of opposite type of conductivity of said drain substrate;i) removing said mask of photo resist; j) activating the implanteddopants by heat treatment; k) forming a spacer along the definition edgesurfaces of at least an aperture destined to the formation of saidSchottky diode there through; l) anisotropic etching of thesemiconductor for a depth deeper than the depth of said body regions,exposing surfaces of said body region and of said drain substrate in azone surrounded laterally by said body regions; m) depositing one ormore conductive metal layers for establishing an electric contact withsaid body region and a good barrier height of the Schottky contactestablished with said drain substrate on at least a portion of thebottom surface of said etching of the semiconductor.
 12. An insulatedgate power device, comprising: a drain region having a firstconductivity type and having a surface; an aperture extending beyond thesurface of the drain region and having sidewalls defined by adjacentfirst and second gate stacks, the gate stacks being electricallyisolated from the aperture; first and second body regions formed in thedrain region with each having a second conductivity type, the first bodyregion having a portion adjoining the first gate stack and a portionadjoining a portion of the aperture, and the second body region having aportion adjoining the second gate stack and a portion adjoining aportion of the aperture; a contact opening formed by a portion of thedrain region defined between the portions of the first and second bodyregions adjoining the aperture; first and second source regions formedin the first and second body regions, respectively, each source regionhaving the first conductivity type and having a portion exposed on thecorresponding sidewall of the aperture; and a metal region formed in theaperture, the metal region contacting the body and source regions andthe contact opening.
 13. The insulated gate power device of claim 12wherein first conductivity type is N-type and the second conductivitytype is P-type.
 14. The insulated gate power device of claim 12 furthercomprising first and second deep body regions formed in the first andsecond body regions, respectively, each deep body region having thesecond conductivity type.
 15. The insulated gate power device of claim12 further comprising a drain engineering implant region formed in thedrain region.
 16. The insulated gate power device of claim 12 whereineach gate stack comprises: an oxide layer formed on a surface of thedrain region; a polysilicon region formed on the oxide layer; aninsulating layer formed on the polysilicon layer; and an insulatingspacer formed on the oxide layer and between the polysilicon andinsulating layers to isolate these layers form the correspondingsidewall of the aperture.
 17. A method of forming an insulated gatepower device including a drain region having a first conductivity typeand having a surface, the method comprising: forming first and secondgate stacks on the surface of the drain region; forming an aperturebetween the gate stacks, the aperture extending beyond the surface ofthe drain region and having sidewalls defined by the gate stacks, theaperture being electrically isolated from the gate stacks; implanting adopant having the second conductivity type at a first angle relative tothe sidewalls of the aperture to form a first body region in the drainregion; implanting a dopant having the second conductivity type at asecond angle relative to the sidewalls of the aperture to form a secondbody region in the drain region, the second body region being formedadjacent the first body region to form a contact opening betweenportions of the first and second body regions adjoining the aperture;forming first and second source regions in the first and second bodyregions, respectively; and forming a metal region in the aperture, themetal region contacting the body and source regions and the contactopening.
 18. The method of claim 17 wherein the operations of implantinga dopant are each performed multiple times to form the first and secondbody regions.
 19. The method of claim 17 wherein the implanted dopanthas a conductivity type that increases the resistivity of the drainregion.
 20. An electronic system including an insulated gate powerdevice, the insulated gate power device comprising: a drain regionhaving a first conductivity type and having a surface; an apertureextending beyond the surface of the drain region and having sidewallsdefined by adjacent first and second gate stacks, the gate stacks beingelectrically isolated from the aperture; first and second body regionsformed in the drain region with each having a second conductivity type,the first body region having a portion adjoining the first gate stackand a portion adjoining a portion of the aperture, and the second bodyregion having a portion adjoining the second gate stack and a portionadjoining a portion of the aperture; a contact opening formed by aportion of the drain region defined between the portions of the firstand second body regions adjoining the aperture; first and second sourceregions formed in the first and second body regions, respectively, eachsource region having the first conductivity type and having a portionexposed on the corresponding sidewall of the aperture; and a metalregion formed in the aperture, the metal region contacting the body andsource regions and the contact opening.
 21. The electronic system ofclaim 20 wherein the electronic system comprises a system that rectifiessignals.
 22. The electronic system of claim 20 wherein the rectifyingsystem comprises a DC-DC converter.